CTMODE=TIMER_MODE, CINSEL=CAP0
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTMODE | Counter/Timer Mode This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 (TIMER_MODE): Timer Mode. Counts every rising PCLK edge 1 (COUNTER_MODE_RISING): Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (COUNTER_MODE_FALLING): Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (COUNTER_MODE_EDGES): Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CINSEL | Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 0 (CAP0): CAP0. CAPn.0 for TIMERn 1 (CAP1): CAP1. CAPn.1 for TIMERn 2 (CAP2): CAP2. CAPn.2 for TIMERn 3 (CAP3): CAP3. CAPn.3 for TIMERn |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |